Ho! No FPGA-reset button on armadeus card.
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That is a constant comment about the armadeus APF9328 board. Most of the FPGA designers learn that it's mandatory to use a reset in each module with structure like it:
myprocess : process (clk,reset) begin if reset = '1' then -- init values elsif rising_edge(clk) then -- processing code end if; end process myprocess;
But by default there is no reset button on the board, then what to do ?
Plug a reset button
Of course it's possible to solder a reset button on card, there are a large amount of I/O on connector and one can be used for this usage.
Generate the reset internally
But it is also possible to use initial state of the FPGA after configuration with this code:
![]() | Warning: This code only work with FPGA, because states of flip-flop after configuration is defined to '0'. This can't work with CPLD for example because beginning state is unknown. |
--------------------------------------------------------------------------- Entity clock_and_reset_gen is --------------------------------------------------------------------------- generic( invert_reset : std_logic := '0' -- 0 : not invert, 1 invert ); port ( -- external signals ext_clk : in std_logic ; --internal generated signals gls_clk : out std_logic ; gls_reset : out std_logic ); end entity; --------------------------------------------------------------------------- Architecture clock_and_reset_gen_1 of clock_and_reset_gen is --------------------------------------------------------------------------- signal dly: std_logic := '0'; signal rst: std_logic := '0'; signal int_reset : std_logic; begin int_reset <= '0'; ---------------------------------------------------------------------------- -- RESET signal generator. ---------------------------------------------------------------------------- process(ext_clk) begin if(rising_edge(ext_clk)) then dly <= ( not(int_reset) and dly and not(rst) ) or ( not(int_reset) and not(dly) and rst ); rst <= ( not(int_reset) and not(dly) and not(rst) ); end if; end process; gls_clk <= ext_clk; gls_reset <= rst xor invert_reset ; end architecture clock_and_reset_gen_1;